Standard memory circuits, according to the prior art, use a common bus to read, write and refresh the bitlines. In FIG. 1, a memory 100 according to the prior art is illustrated. Memory 100 includes two columns of memory cells, bitline column 101 and bitline column 102. Each bitline includes a plurality of memory cells for the storage of data. For ease of illustration, bitline column 101 and bitline column 102 are each shown to include four memory cells, memory cells 103-106 in bitline column 101, and memory cells 107-110 in bitline column 102.
Prior to any read or write operation, the bitlines arc precharged to V.sub.DD. Precharge is initiated by asserting bitline precharge signal 111 thereby turning on p-type metal oxide semiconductor (PMOS) devices 112-114 in precharge circuit 115, and PMOS devices 116-118 in precharge circuit 119, respectively. PMOS device 114 equalizes bitlines 120 and 121 which are then pulled to V.sub.DD through PMOS devices 112 and 113. Similarly, bitlines 122 and 123 are equalized by PMOS device 118 and pulled to V.sub.DD by PMOS devices 116 and 117, respectively.
The precharge rate is limited by the capacitance on the bitlines. This limits the cycle time for memory 100. The capacitance on the bitline arises from the bitline wire capacitance and the capacitance of the semiconductor devices within the memory cells 103-106, and 107-110. As the number of cells on a bitline increases, the capacitance increases proportionately. Thus, as the size of memory 100 increases, the cycle time also increases as well.
After the bitlines are precharged, bitline precharge signal 111 is negated, turning off PMOS devices 112-114, and 116-118. Data can then be read from, or written to, one of memory cells 103-110. For a write operation, a data value on Data In line 124, and its complement on Data In line 125 are transferred to bitlines 120 or 122 and 121 or 123, respectively, via n-type metal oxide semiconductor (NMOS) devices 126, 127, 128 and 129. Data is transferred in response to a write select signal asserted on write select 130 if the write is to be made to one of memory cells 103-106 in bitline column 101, or on write select 131 if a write is to be made to one of memory cells 107-110 in bitline column 102. Asserting the write select signal on write select 130 turns on NMOS devices 126 and 127, and asserting a write select on write select 131 turns on NMOS devices 128 and 129. The turning on of NMOS device 126 couples Data In 124 to bitline 120, and the complimentary data value on Data In 125 to bitline 121. Similarly, asserting write select 131, thereby turning on NMOS devices 128 and 129, couples Data In 124 to bitline 122 in bitline column 102, and the complementary data value on Data In 125 to bitline 123 in bitline column 102. Depending on the data value, one of Data In 124, and Data In 125 is logic "1" and the complementary input is logic "0." The coupling of bitlines 120 and 121 to Data In 124 and Data In 125, respectively, if write select 130 is asserted, or bitlines 122 and 123 to Data In 124 and Data In 125, respectively, if write select 131 is asserted, discharges the precharge on the bitlines. The one of bitlines 122 and 123 that is coupled to the one of Data In 124 or Data In 125 that is logic "0" is discharged to ground. Thus, the write operation also requires discharging of the capacitances appearing on the bitlines, and therefore, the write time performance of the memory is also limited by the bitline capacitance.
Hence, there is a need in the art in which the bitline capacitances that the precharge circuitry is required to charge during the precharge operation, or the write circuitry is required to discharge during a write operation, are reduced. The reduction of this capacitance improves the performance of such memory by reducing the precharge time, and the time required to write to such memory, permitting faster memory cycle rates.